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| analog devices fax-on-demand hotline analog w devices i preliminary technical data features 300 ksps throughput rate 16-bit sampling adc self-calibration high-speed parallel interface 90 db signal-to-noise ratio low power: 200 mw typ 500 ~iw typ in power-down mode unipolar and bipolar input signal ranges on-chip 2.5 v reference operates from :t5 v supplies applica tions data acquisition systems digital signal processing spectrum analysis dsp servo control general description the ad7882 is a fast, 16-bit self-calibrating aid converter. it consists of a sample-and-hold amplifier, a self calibrating 16-bit adc, a 2.5 v reference and versatile interface logic. an on-chip controller manages the self-calibrating algorithm which reduces linearity, offset and gain errors to :!:.0015 %. system offset and gain errors, caused by external conditioning circuitry, can also be included in the calibration procedure. throughput is maximized at 300 ksps by the use of a dual sample-and-hold amplifier. the adc also has a self- contained internal dock which is laser trimmed to guarantee accurate control of conversion time; alternatively, an external dock may be used. another feature of the ad7882 is a power-down mode which reduces power dissipation from its normal operating value of 200 mw to 0.5 mw. the ad7882 operates from :!:5 v supplies. analog input ranges can be unipolar, 0 to 2.5 v or bipolar, :!:2.5 v. the analog input bandwidth is 200 khz. in addition to traditional dc accuracy specifications such as linearity, the ad7882 is also fully specified for dynamic per- formance parameters induding harmonic distortion and signal-to-noise ratio (snr). the ad7882 is fabricated in analog devices' linear compat- ible cmos (lc2mos), an advanced, mixed technology proc- ess that combines precision bipolar circuits with low-power high-speed cmos logic. the part is available in a 44-pin plastic quad flat pack (pqfp) and 40-pin cerdip. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. 2 lc2mos 16 - bit, 300 ksps, sampling adc ad7882 i functional block diagram c>ef1 cref> dvdd a'n vrefi avdd vrefout agnd dgnd clkln pid w1i m/s st!!i" ~ elp/up convst busy dea avss de.. product highlights 1. fast 300 ksps throughput rate. a fast 300 ksps throughput rate makes the ad7882 suitable for a wide range of data acquisition applications. 2. self-calibration achieves high accuracy a self-calibrating algorithm minimizes linearity, offset and gain errors. the calibration procedure can also include external offset and gain errors. 3. dynamic specifications for dsp users. in addition to traditional dc specifications, the ad7882 is specified for ac parameters including signal-to-noise ratio and harmonic distortion. these parameters along with im- portant timing parameters are tested on every device. 4. fast, versatile microprocessor interface. fast bus access times and standard control signals make the ad7882 easy to interface to microprocessors. 5. low power. low power monolithic solution allows ease of application. the ad7882 also has a power down facility one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 prelim.f 3/95 obsolete
analog devices fax-on-demand hotline 3 ad7882 specifications (avoo = 5v :1:5%. dvoo = 5v :1:5%. avss = -5v :1:5%. vrefin = 2.5v. - agnd = dgnd = 0 v. fclkin = 10 mhz. fsample = 300 khz. all specifications tmih to tmax unless otherwise noted.) no1fs j temperarure ranges are as follows: a, b version -40c to 85c s, tversion-55cto 125c 2 specifications apply after calibration. j sample tested at 25c to ensure compliance. specifications subject to change without notice. prelim.f 3/95 a,s b,t parameter version! version! units test conditions/comments dynamic performance" signal to(noise+distortion ratio) 90 90 db min ai)! = 10khz, typical snr = 92 db 85 85 db min ai)! = 100 khz, typical snr = 87 db thd -95 -95 db max ai)! = 10khz, typical thd = -100 db -88 -88 db max ai)! = 100 khz, typical thd = -90 db peak harmonic or spurious noise -98 -98 db max ai)! = 10khz, typical peak har. = -100 db -90 -90 db max ai)! = 100 khz, typical peak har. = -92 db intermodulation distortion 2)!d order terms -88 -88 db max fa = 98 khz, fd = 100khz 3rd order terms -88 -88 db max throughput time 3.3 3.3 j.1s max aperture delay 10 10 ns typ aperture jitter 20 20 ps typ noise 70 70 j.1v rids typ dc accuracy" resolution 16 16 bits minimum resolution for which no missing codes guaranteed 16 16 bits integral nonlinearity 1:1/2 1: 112 lsb typ integral nonlinearity 1: 1.0 lsb max differential nonlinearity 1:0.9 1:0.5 lsb max unipolar offset error 1:2 1:2 lsb max unipolar gain error 1:2 1:2 lsb max bipolar zero error 1:2 1:2 lsb max bipolar positive gain error 1:2 1:2 lsb max bipolar negative gain error 1:2 1:2 lsb max power supply rejection avdd only 84 84 db typ a v 55 only 84 84 db typ analog lip input current 1:1 1:1 ilamax input range = 0 - 2.5 v or 1: 2.5 v input capacitance 3 20 20 pf max reference output vrefout @ 25c 2.5 2.5 volts nominal 1:1% vrefout tempco 20 20 ppm/oc typ reference input v rei'i)! range 2.5 2.5 volts 1:2% v rei'i>l current 1:1 1:1 ilamax logic inputs input high voltage, vi>lh 2.4 2.4 volts min input low voltage, vi>ll 0.8 0.8 volts max input current 1:10 1:10 ilamax input capacitance3 10 10 pf max sleep input input high voltage, vi>lh vdd - 0.2 voo - 0.2 volts min input low voltage, vi)!! 0.2 0.2 volts max clkin input negative trigger level -2 -2 volts min this is the trigger level for choosing internal clock operation of the device obsolete analog devices fax-on-demand hotline ~ i preliminary technical data ad7882 i ad7882 specifications (avdd = 5v :5%. dvdd = 5v :5%. avss = -5v :5%. vrefin = 2.5v. - agnd = dgnd = 0 v. fclkin = 10 mhz. fsample = 300 khz. all specifications tmin to too unless otherwise noted.) ncjies 1 temperature ranges are as follows: a, b version -40c to 85c s, tversion-55cto 125c 2 specifications apply after calibration. j sample tested at 2soc to ensure compliance. specifications subject to change without notice. - 3 - prelim.f 3/95 a,s b,t parameter version1 versionl units test conditions/comments logic outputs output high voltage, voh 2.4 2.4 volts min isource = 200 j.!a output low voltage, vol 0.4 0.4 volts max is!)!( = 1.6 ma dbi5 - dbo tri-state leakage current flo flo j.!amax tri -state output capacitance 3 20 20 pf max power requirements dvdd +5 +5 volts f5 % avdd +5 +5 volts f5 % avss -5 -5 volts f5 % normal mode didd i i ma max aidd 29 29 ma max alss 27 27 ma max power dissipation 300 300 mw max typically 200 mw. clkin not running sleep mode didd 40 40 ita max aidd 50 50 ita max aiss 40 40 ita max power dissipation i i mw max typically 500 j.! w. input logic levels of 0.2v and vdd - 0.2v. clkin not running. typically 1.5mw with clkin running obsolete analog devices fax-on-demand hotline ad7882 5 timing specifications 1 (avdd = 5 v ::1:5 %. dvdd = 5 v ::1:5 %. avss = -5 v ::1:5 %. vrefin = 2.5 v. agnd = dgnd =0' fclkin = 10 mhz. fsample = 300 khz. all specifications tmin to tmax unless otherwise noted. parameter t1 t2 t3 t4 t5 t6 t7 tconvert tsmvlple t8 t9 tlo t11 t122 t133 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 tcal 1 tcal 2 tcal 3 tcal 4 limit @ 25c (all versions) 10 5 10 5 30 30 5 30t clkin 3.0 33t clkin 3.3 30 20 0 0 40 40 10 75 10 5 40 20 10 0 30 20 20 9276744 t clkin 6359324 t clkin 1475104 tclkin 1442324 t clkin limit@tmin, tmax (a,b versions) is 5 is 5 40 40 5 30t clkin 3.0 33t clkin 3.3 40 30 0 0 50 50 10 75 is 5 40 30 20 0 40 30 30 limit@tmin, tmax (s,tversions) 20 10 20 10 50 50 10 30t clkin 3.0 33t clkin 3.3 50 40 0 0 60 60 10 75 20 10 50 40 30 0 50 40 40 units nsmm nsmin nsmm nsmin nsmin nsmm nsmm fig max fig max nsmin ns max nsmm nsmin nsmin ns max nsmin ns max nsmin nsmin nsmm ns max nsmin nsmin nsmm s max ns max conditions/comments addo to wr setup time addo to wr hold time cs to wr setup time cs to wr hold time wr pulse width data setup time data hold time conversion time: synchronous operation conversion time: internal clock operation time between samples: synchronous operation time between samples: internal clock operation convst pulse width convst high to busy low delay cs to rd setup time cs to rd hold time rd pulse width rd low to data valid delay (data access time) data hold time after rd (bus relinquish time) addo to rd setup time addo to rd hold time new data valid before rising edge of busy clkin falling edge to busy low delay cs to cal setup time cs to cal hold time cal pulse width ca[ high to busy low delay convst high to busy low delay: system cal mode device calibration time: device cal mode dac calibration time: system cal mode otiset calibration time: system cal mode gain calibration time: system cal mode notes lab input signals are specified with tr= tf= 5ns (10% to 90% of 5v) and timed from a voltage level of 1.6v. \3 is measured with the load circuit of figure 1 and defined as the time required for an output to cross 0.8v or 2.4v. 3 t]4 is derived from the measured time taken by the data outputs to change 0.5v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 100pf capacitor. this means that the time, tl4' quoted in the timing specifications is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. specifications subject to change without notice ad7882 ordering guide 1 q=cerdip s = pqfp - 4 - prelim.f 3/95 model temperature integral nonlinearity package range (lsb's) option' ad7882sq -55c to +125c :to.5 typ q-40 ad7882tq -55c to +125c :tl max q-40 ad7882as -40c to +85c :to.5 typ s-44 ad7882bs -40c to +85c :tl max s-44 obsolete analog devices fax-on-demand hotline 6 ad7882 i i preliminary technical data os addo .2.1v wr db15. dbo tfi figure 1. load circuit for bus access and relinquish time figure 2. write timing diagram analog input sampled convst tsample -q tconvert j busv cs ,t11 ad ob15-0bo ~ ~ ,. vau~. t- aooo address - valid ".~. t14 figure 3. read timing diagram, asynchronous operation (mis - low; cal = high) analog input sampled tsample ~ convst i tot tconvert ~ / busy ~ -.-t17 db15 - dbo old data x new data figure 4. read timing diagram, asynchronous operation (mis, cs, rd, addo - low; cal - high) - 5 - prelim.f 3/95 obsolete analog devices fax-on-demand hotline 7 ad7882 analog input (t,,) \ sampled i analog input (~...) sampled clkin ~v~ycn' - db15 0 dbo data (n 01) - )$ data (n01x -- t17 data (n) )~ .~~ .~5 / )$ data(n) ~ta(n+1) busv ~~ i i figure 5 read timing diagram, synchronous operation (cs, rd - low; mjs, cal = high) start of calibration t19 cs t21 m t22 tcal 1 . busy figure 6. device calibration timing (mjs - low; rd, wr - high) t19 start of dac calibration cs cal t21 ~i start of offset calibration start of gain calibration "-, ~,- ~, -it ~~ , j t" - -t t,~, 1- '-: t"" ~,- convst busy figure 7 system calibration timing (mjs = high; rd, wr = high) - 6 - prelim.f 3/95 obsolete cerdip pinout 8 i preliminary technical data absolute maximum ratings' (t a = +2s"c unless otherwise noted) avdd to agnd 0.3v to +7v avss to agnd +0.3v to -7v agnd to dgnd 0.3v to 0.3v avdd to dvdd 0.3v to + 0.3v analog inputs to agnd a vss- 0.3v to a vdd+ 0.3v reference inputs to agnd a vss- 0.3v to a vdd+ 0.3v digital inputs to dgnd 0.3v to dvdd+0.3v digital outputs to dgnd 0.3v to dvdd+0.3v operating temperature range commercial plastic (a,b versions) 40"c to +8s"c extended hermetic (s,t versions) -ss"c to + 12s"c storage temperature range 6soc to +isooc junction temperature iso"c lead temperature (soldering, 10 secs) +300"c cerdip package, power dissipation l ooomw ala thermal impedance 50"c/w ad7882 i lead t em pera lure ,so idering vaporphase(60 secs) +21s"c infrared(is secs) +220c pqfppackage, powerdissipation 875mw ala thermal impedance 7s"c/w lead temperature, soldering vapor phase (60 secs) +21soc infrare(1s secs) +22doc notes 1. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operntional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. transient currents of up to 1 ooma will not cause scr latch-up. caution: esd (electro-static discharge) sensitive device. electrostatic charges as high as 4000y, which readily accumulate on the human body and on test equipment, can discharge without detection. although devices feature proprietary esd protection circuitry, pennanent damage may still oc- cur on these devices if they are subjected to high energy electrostatic discharges. therefore, proper precautions are recommended to avoid any perfonnance degradation or loss of functionality. clkin 1 sleep 2 agnd 1 3 agnd 2 4 agnd 3 5 ~eft 6 caef2 7 v vaefin 8 refojt 9 avoo 10 avoo 11 pqfp pinout i ~ 12, gz > c> "' ., ~ ~ i~ ~ ~ i~ ~ ~ ~ ~ ~~~;;:~~~[;~~~ """"'"'~""""'c>~"" ~~~~~~~~"""""" ~~r""~a;~&j~:b~ ~;;: -e.fo 0 0 cds o1s 33 db13 32 db12 31 db11 30 dvdd 29 dvdd 28 dgnd 27 oond 26 db10 25 db9 24 db8 23 db7 analog devices fax-on-demand hotline bos'y ' convst mis 4 bip/of clkin 0 sleep agnd 1 8 agnd 2 - agnd 3 [! cref1 e cref2 ii!: vrefin ie vrefojt e avdd @ avss : ain 1 @: ain 2 ita ad?bb2 dip top view (not to scale) dbo ~ db1 ~ - 7 - analog devices fax-on-demand hotline 10 timing and control clkin clock input, an external ttl-compatible clock may be applied to this input pin. alternatively, tying this pin to a vss enables the internal clock oscillator. this output indicates converter status. busy is low during conversion and calibration. conversion start. a low to high transition on this logic input pin, when the ad7882 is configured for asynchronous operation, places the sample-and-hold amplifier in the hold mode and starts conversion. bipolarlunipolar select logic input. a logic high selects the bipolar input range, (ai:-i range =:t vren:-l) and a logic low selects the unipolar range, (t\:-i range = 0 to vren:-l). sleep function, active low logic input. once asserted, the ad7882 enters the low-power mode. all internal circuitry including the internal voltage reference is powered down. calibration data is retained. active low logic input. a logic low on this input resets all internal logic and initiates a calibration. initiating a calibration overrides all other internal operations and if a conversion is in progress, it will be terminated. mode/sync logic input. this is a dual function pin. when the device is in the cal mode (cal input low), it determines the calibration mode. when the device is in the normal operating mode, it determines whether conversion is synchronous or asynchronous. synchronous operation means that the device continuously converts the input in synchronism with the clock. asynchronous operation means that the device converts the analog input in response to the application of a convst signal. see table i for the cal, m/s truth table. note that the control register can be used to disable this input pin. see control register section. cs addo wr dbl5-dbo busy convst bip/up sleep cal mis outputs. chip select, active low logic input. the device is selected when this input is active. address input. this control input determines whether the word placed on the output data bus during a read operation is an adc conversion result or the contents of the control register. a logic low accesses a conver sion result while a logic high accesses the control register. when writing, if addo is high, the control register is the destination. if addo is low, the calibration data memory is the destination. write, active low logic input. this input is used in conjunction with cs and addo to write data to the ad7882. three-state data outputs which are controlled by cs and rd. data output coding is 2's complement binary. table i. ad7882 operarlng modes - 9 - prelim.f 3/95 cal. mis funcrlon i 0 asynchronous operation i i synchronous operation 0 () device c.alldranon 0 i system calibration obsolete analog devices fax-on-demand hotline ad7882 circuit description analog input the analog input circuitry includes two shas in a ping-pong configuration as in figure 8. the shas alternatively acquire the analog input and hold the output constant for the adc conversions. during conversion, one of the shas is in the hold mode while the other is in the sample mode. the sample figure 8. input sha configuration and hold states are then switched after every conversion. the benefit of this configuration is to eliminate the need for acqui- sition time between conversions. the throughput time is now effectively equal to the conversion time which is 3.0 ~ls.the analog input range can be either unipolar or bipolar depend- ing on the status of the bipfup input. the transfer function for the unipolar range is straight binary while the transfer function for the bipolar input is 2s complement. these are shown in figures 9 and 10. oulput code 1111...111 1111...110 ./ 1111...101 1111...100 ." 0000...011 i lsb . fsi~o 0000...010 1--0 fs 0000...001 vin,lnpulvolage (lsbs) ~ t 0000...000 figure 9. fs .1lsb unipolar transfer function ootput cooe 0111..111 0111..110 0000..011 0000...010 0000..001 0000..000 1111..111 ~"lsb 2 1111..110 1000.010 1 ls.'f~'" 1000...001 1000.000 figure 1 o. v",ln~""'age(lsbs) bipolar transfer function 11 calibration the ad7882 conversion procedure is based on the successive approximation algorithm. accuracy of the individual compo- nents, such as the dac and comparator, is critical to achieve 16-bit performance. the comparator uses an auto-zero tech- nique to null both internal and external offsets. another ad- vantage of this scheme is that it nulls 1/fnoise. the auto-zero s\vitching occurs well above the iff roll-off frequency, thus the noise appears as a dc offset which gets cancelled. the internal dac uses binary weighted capacitors instead of the traditional r-2 r ladder type. this allows the ad7882 to employ a calibration routine which nulls the errors of the in- dividual dac segments along with offset and gain errors. each segment of the capacitor dac contains multiple capaci- tors which are used to trim for absolute accuracy. during a . calibration routine, the dac segments are compared against other segments and trimmed to 1/4 lsb accuracy. offset and gain errors are then calibrated either against the device agnd and v reri~ inputs or external reference voltages that are applied at the ~~ input. calibration routine the ad7882 is capable of two calibration methods; system calibration and device calibration. both modes calibrate the internal dac linearity along with offset and gain errors. a system calibration is where the device calibrates its full scale and offset voltages against externally applied voltages. for a device calibration full scale and offset are calibrated against the vreri~ and agnd inputs. note that a calibration must always be initiated after power on to meet the device performance specifications. calibration may be initiated in hardware by asserting the cal pin or in software by writing the appropriate word to the control register. the ad7882 will always perform a full calibration if initiated in hardware. however, under software control, partial calibration options including only offset and gain, can be performed. these options are shown in table iii. device calibration device calibration is initiated by pulsing cal low; see figure 6. offset and gain are calibrated against the agnd and vreri~ inputs respectively. this calibration procedure takes 928 ms, when using a 10 mhz clock. system calibration system calibration is initiated by a positive edge on cal as shown in figure 7. busy goes low three times during the calibration procedure corresponding to the dac, offset and gain calibrations respectively. the rising edge of the first busy pulse indicates that the dac calibration is complete and the ad7882 is now ready to calibrate the offset. this is achieved by applying an external 0 v input at the ~~ input and asserting the convst input. note, the external 0 v input must be within :i:1.5 % of agnd. the rising edge of the second busy pulse indicates that the part is ready to calibrate full scale. this time, the full scale input voltage must be applied to the analog input and convst must be - 10 . prelim.f 3/95 obsolete analog devices fax-on-demand hotline 12 i preliminary technical data asserted once again. the full-scale input voltage must be within :t1.5 % of the reference input voltage. complete cali- bration time is 928 ms plus the width of the two convst start pulses, when using a 10 mhz clock for the device. configuring the mis input the mis input with conjunction with the cal input determines the type of calibration iniated when cal is taken low. it also determines whether the conversion is asynchronous (controlled by the convst input) or synchronous (with clkin). in all, they can be configured in four different ways as shown in figure ii. the cal input is firure 11. mis input configuration asserted by a positive edge, when calibration is required. then, for example if synchronous operation and device cali- bration is required, mis is tied to cal. note, an inverter can be used between the cal and the mis inputs when asyn- chronous operation and system calibration is required. if cal is high, then the user can start a calibration from the control register. timing and control data communication with the ad7882 is controlled by four control inputs; cs, rd, wr and addo. the data transfer consists ofreading and writing to the control register or coef- ficients register and reading the conversion result from the output data register. conversion control and data reads conversion can be controlled in hardware by asserting the convst input (asynchronous mode) or the device can be set up for continuous "back-to-back" conversions (synchronous mode). the mis input controls these as outlined above. in synchronous mode, a power-up, cal or -- --~ ad7882 convst will initiate operation. the data outputs are controlled by the cs and rd inputs. the possible timing configurations are shown in figures 3, 4 and 5. if cs and rd are tied permanently low then the data bus will always be active. however, it will change state at the end of conversion to reflect the most recent result. reading the data bus must be avoided at this time. control register the control register serves the dual function of providing control and monitoring the status of the ad7882. this register is directly accessible through the data bus with a read or write operation while addo is high. one of the option settings in the control register is to set up the coefficients register for reading or writing. the coefficient registers contain the calibration coefficients. loading the coefficients to the register consists of writing 40, 16-bit words. this activity is considerably shorter for almost any processor than performing a calibration. thus, a typical application might read all the coefficients after calibration, store them in the backup memory and rewrite them to the ad7882 in future power-up initialization routines. reading the calibration co- efficients consists of 40 read cycles to the ad7882. this will return 40, 16-bit words to the microprocessor. writing to the ad7882 data can be written to either the control register or the coeffi- cients register. a typical timing diagram is shown in figure 12. addo < > valid cs w'r db15. dbo figure 12. typical write timing - 11 prelim.f 3/95 calibiation device sy.;;tero c.liblotion c.liblotion ", "1' 0 c.;l h/o ol .:: 0 0 2 lj 0 0 -rl lj +j .c !o g - " : q) "' 8' 'c -< " g g c.'l "1'0 c.'l 11/0, " 0 0--0 ljo -j .c u lj : '.' obsolete analog devices fax-on-demand hotline 13 ad7882 table ii. conttol register bitfunctions function conversion status. this bit is high during conversion. calibration status. this bit is high during calibration. bip/up select. unipolar operation is selected when cr2 is 0; bipolar operation is selected when cr2 is i. this assumes that cr3 is i. when cr3 is 0, cr2 reflects the elp/up input. if cr3 = 1 then control register bits cr2, cr9 and crio have priority. otherwise external pins, sleep and elp/up have priority. cr4 to cr7 determine the calibration function, see table iii. calibration function, see cr4. calibration function, see cr4. calibration function, see cr4. not used sleep control bit. when cr3 is i, setting cr9 to 0 powers down all circuitry except the reference. when cr3 is 0, cr9 reflects the state of the sleep input. reference power down. when cr3 is i, reference is powered by writing a 0 to crio. when cr3 is 0, crio reflects the state of the sleep input. a i in this location indicats an overflow on ae-l in the last conversion and a gain adjust is required to bring the input back within range. a i in this location indicats an underflow on a])i in the last conversion and a gain adjust is required to bring the input back within range. not used status bit. if this is i, it means that the calibration is halted. calibration can be continued by writing a 0 to this location. reset bit. all memory and logic is reset when a 0 is written to this location. reset happens on the rising edge of wr. if there is a subsequent control register read all bits except cri5 will have power-up default setting. therefore, to restart after a software reset, it is necessary to write a 1 back into cri5. - 12 - prelim.f 3/95 - power-up bit location i/o option default cro read only 0 cri read only 0 cr2 readlwrite bip/up cr3 read/write 0 cr4 readlwrite 0 crs readlwrite i cr6 readlwrite i cr7 read/write i cr8 cr9 read/write sleep crio read/write sleep crll read 0 cri2 read 0 cr13 cri4 read/write 0 cri5 read/write table iii. calibration options using the conn'ol register. cr7 cr6 cr5 cr4 function 0 0 0 0 normal conversion, no calibration 0 0 0 1 normal conversion, no calibration 0 0 i 0 gain error only - device calibration 0 0 1 1 gain error only - system calibration 0 1 0 0 offset error only - device calibration 0 i 0 1 offset error only - system calibration 0 i i 0 offset and gain error only - device calibration 0 i 1 i offset and gain error only - system calibration i 0 0 0 read all calibration coefficients 1 0 0 1 write all calibration coefficients 0 1 0 read gain calibration coefficients only 0 i 1 write gain calibration coefficients only i 0 0 read offset calibration coefficients only i 0 1 write offset calibration coefficients only 1 1 0 full device calibration i 1 1 full system calibration obsolete |
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